by Jack Goho
Gideon Analytical Laboratories received a programmable logic device (PLD) P18586P for failure analysis. A programmable logic device is an electronic component used to build reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be used in a circuit it must be programmed. A PLD is a combination of a logic device and a memory device. The memory is used to store the pattern that was given to the chip during programming. Most of the methods for storing data in an integrated circuit have been adapted for use in PLDs. Logic devices provide specific functions, including device-to-device interfacing, data communication, signal processing, data display, timing and control operations, and almost every other function a system must perform. The PLD P18586P supposedly had bad output. The goal was to determine the reason why.
Failure analysis was conducted on the PLD P18586P. The intermittency problem could not be reproduced. The PLD was opened the circuitry inspected for electrical overstress (EOS) and/or electrostatic discharge (ESD). EOS is a term used to describe the thermal damage that may occur when an IC is subjected to a current or voltage that is beyond the datasheet specification limits of the device. ESD is a transient discharge of static charge between two objects at different electrostatic potentials either through direct contact or an induced electric field. There was a disruption in the logic portion of the PLD not too far from the Vdd rail. The failure site appeared to be a result of ESD. Another difference between ESD and EOS is the speed at which the voltage propagates. ESD can travel through the entire circuity and end up anywhere on the die, whereas, EOS is typically a confined event. This ESD initial damage probably occurred prior to being placed on the printed circuit board (PCB). The output had to be unreliable from its initial occurrence.
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